Pregled bibliografske jedinice broj: 1204056
Discrete Cosine Transform Hardware Accelerator in Parallel Ultra-low Power System
Discrete Cosine Transform Hardware Accelerator in Parallel Ultra-low Power System // 63rd International Symposium ELMAR-2021
Zadar, Hrvatska, 2021. str. 169-172 doi:10.1109/ELMAR52657.2021.9550946 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
CROSBI ID: 1204056 Za ispravke kontaktirajte CROSBI podršku putem web obrasca
Naslov
Discrete Cosine Transform Hardware Accelerator in
Parallel Ultra-low Power System
Autori
Duspara, Alen ; Kovač, Mario ; Mlinarić, Hrvoje
Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni
Izvornik
63rd International Symposium ELMAR-2021
/ - , 2021, 169-172
Skup
63rd International Symposium ELMAR-2021
Mjesto i datum
Zadar, Hrvatska, 13.09.2021. - 15.09.2021
Vrsta sudjelovanja
Predavanje
Vrsta recenzije
Međunarodna recenzija
Ključne riječi
JPEG ; DCT ; HERO ; PULP ; HESoC ; PMCA
Sažetak
In this paper, the architecture of a fully pipelined discrete cosine transform (DCT) hardware accelerator for a JPEG encoder is proposed. The integration of the accelerator into the parallel ultra-low power (PULP) platform is also demonstrated. The accelerator architecture is divided into two one-dimensional transform cores with one transpose buffer between them. With the designed accelerator, it is possible to calculate one 2D DCT operation in 32 cycles with a latency of 80 cycles. The JPEG DCT hardware accelerator is integrated into the PULP cluster as a separate processing element (PE) and successfully implemented on the Xilinx ZC706 evaluation board. The accelerator can achieve the performance of up to 1.78M transformations per second working on the clock frequency of 57 MHz.
Izvorni jezik
Engleski
Znanstvena područja
Računarstvo
POVEZANOST RADA
Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb
