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Abdi, Samar ; Schirner, Gunar ; Yonghyun Hwang ; Gajski, Daniel D. ; Lochi Yu
Automatic TLM Generation for Early Validation of Multicore Systems // IEEE design & test of computers, 28 (2011), 3; 10-19. doi: 10.1109/MDT.2010.117
Trajkovic, Jelena ; Gajski, Daniel D.
Early performance-cost estimation of application- specific data path pipelining // Proceeding of IEEE 8th Symposium on Application Specific Processors (SASP), 2010. Institute of Electrical and Electronics Engineers (IEEE), 2010. str. 107-110
Yonghyun Hwang ; Schirner, Gunar ; Abdi, Samar ; Gajski, Daniel D.
Accurate timed RTOS model for transaction level modeling // Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. Institute of Electrical and Electronics Engineers (IEEE), 2010. str. 1333-1336
Abdi, Samar ; Yonghyun Hwang ; Lochi Yu ; Hansu Cho ; Viskic, Ines ; Gajski, Daniel D.
Embedded system environment: A framework for TLM- based design and prototyping // Proceedings of 21st IEEE International Symposium on Rapid System Prototyping (RSP), 2010. Institute of Electrical and Electronics Engineers (IEEE), 2010. str. 1-7
Abdi, Samar ; Schirner, Gunar ; Viskić, Ines ; Hansu, Cho ; Yonghyun, Hwang ; Lochi, Yu ; Gajski, Daniel D.
Hardware-dependent Software synthesis for many-core embedded systems // Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC 2009). Institute of Electrical and Electronics Engineers (IEEE), 2009. str. 304-310
Gajski, Daniel D.
System-level synthesis: From specification to transaction level models // Proceedings of International Conference on Communications, Circuits and Systems, 2009. ICCCAS 2009.. Milpitas (CA): Institute of Electrical and Electronics Engineers (IEEE), 2009. str. 1134-1138
Coussy, Phillipe ; Gajski, Daniel D. ; Meredith, Michael ; Takach, Andres
An Introduction to High-Level Synthesis // IEEE design & test of computers, 26 (2009), 4; 8-17. doi: 10.1109/MDT.2009.69
Gajski, Daniel D. ; Abdi, Samar ; Gerstlauer, A. ; Schirner, G.
Embedded system design: modeling, synthesis and verification. New York (NY): Springer, 2009
Shin, Dongwan ; Gerstlauer, A. ; Domer, R. ; Gajski, Daniel D.
An Interactive Design Environment for C-Based High- Level Synthesis of RTL Processors // IEEE transactions on very large scale integration (VLSI) systems, 16 (2008), 4; 466-475. doi: 10.1109/TVLSI.2007.915390
Reshadi, Mehrdad ; Gorjara, Bita ; Gajski, Daniel
C-based design flow: A case study on G.729A for Voice over internet protocol (VoIP) // Proceedings of 45th ACM/IEEE Design Automation Conference, 2008. DAC 2008.. Anaheim (CA), 2008. str. 72-75