LAPA, a 5 Gbps modular pseudo-LVDS driver in 180 nm CMOS with capacitively coupled pre-emphasis (CROSBI ID 674351)
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Podaci o odgovornosti
Cardella, R. ; Berdalovic, I. ; Egidos Plaja, N. ; Kugathasan, T. ; Marin Tobon, C. A. ; Pernegger, H. ; Riedler, P. ; Snoeys, W.
engleski
LAPA, a 5 Gbps modular pseudo-LVDS driver in 180 nm CMOS with capacitively coupled pre-emphasis
A pseudo-LVDS driver has been designed in a 180 nm technology for operation up to 5 Gb/s. It contains parallel main driver units based on an H-bridge circuit steering a current on an external load. The number of active units is adjustable, to reduce switching capacitance and static current, and hence power consumption, if a smaller current swing can be tolerated. Pre-emphasis is applied with a capacitively coupled charge-injection circuit. In the nominal condition with a steering current of 4 mA over a 100 Ω termination resistor, it consumes 30 mW from a 1.8 V supply.
Depleted monolithic CMOS pixels ; particle tracking detectors (solid-state detectors) ; VLSI circuit
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Podaci o prilogu
038
2018.
objavljeno
10.22323/1.313.0038
Podaci o matičnoj publikaciji
Sissa Medialab
Podaci o skupu
Nepoznat skup
poster
29.02.1904-29.02.2096