engleski

Programmable Digital IC for Sub-Nanosecond Dead- Time Adjustment Used in Synchronous Switching DC- DC Converters

A digital integrated circuit for sub-nanosecond dead-time adjustment is designed and its operation principle is described. The designed dead-time adjustment circuit (DTAC) generates two complementary control signals for the FET switches used in synchronous switching DC-DC converters. The control signals are generated from a PWM signal that is provided at the input of the DTAC. The circuit is based on a tapped delay-chain architecture and it is designed for the switching frequencies up to 10 MHz. The DTAC is designed in a 0.18-μm CMOS process. The impact of the process variations, ambient temperature and supply voltage on the achievable time-delay is investigated by the post-layout simulations. Additionally, the on- chip digital ‘slave’ circuit for serial communication is designed to allow programmability of the DTAC.

post-layout simulations ; SPI communication ; tapped delay-chain ; synchronous buck converter

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