engleski

A Learning Tool for Synthesis, Visualization, and Editing of Programming for Simple Programmable Logic Devices

Our experiences in teaching digital circuit design at university level indicate that students find it difficult to understand programmable logic devices (PLDs) such as PALs, PLAs, GALs and FPGAs. This is mainly due to the complexity of the topic and the lack of tools that visualize the inner workings of PLDs and enable students to modify and inspect individual components. The majority of publicly available SPLD-related tools are proprietary, platform-specific and do not expose all elements of the PLD structure to the user. In this work, we propose a learning tool that enables synthesis, visualization and editing the programming of a GAL16v8 SPLD. GAL16v8 has been chosen as it is simple enough that its physical implementation can be observed to the smallest detail, while enabling simultaneous realization of multiple Boolean functions. The tool is platform-independent and specifically tailored towards use in an educational setting, facilitating much better understanding of SPLDs through a hands-on experience.

digital circuit design, PLD structure, learning tool for GAL16v8

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