engleski

On-chip Interconnect Inductance Extraction and Analysis

With increasing speed of VLSI circuits parasitic inductance of interconnect becomes ever more important. There are simple 2D models for inductance extraction. The way to accurately calculate inductance is to use partial inductances a full 3D problem. For later electrical simulation it is important to decrease size and/or density of the partial inductance matrix. It can be done by using port inductances or some sparsification method. This paper presents partial inductance concept and methods for inductance extraction and modelling.

inductance; partial inductances; interconnect

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