engleski

Time Delay Testing in the Programmable Logic Circuit Design

The paper discusses timing delays which exist in Programmable Logic Devices (PLD) high-speed circuits applications. The statistical results of time delay measurements are applied in reliability analysis to predict the Mean Time Between Failure (MTBF) in PLD logic circuits design. It is shown that propagation (time) delay optimisation in design procedure has a marked effect on the PLD timing reliability characteristics. A good design approach would be to use macrofunction library structures rather than to create own cross-coupled implementations with primitives.

time delay; bistable; pld; testing

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