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Accurate timed RTOS model for transaction level modeling (CROSBI ID 597922)

Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija

Yonghyun Hwang ; Schirner, Gunar ; Abdi, Samar ; Gajski, Daniel D. Accurate timed RTOS model for transaction level modeling // Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010. Institute of Electrical and Electronics Engineers (IEEE), 2010. str. 1333-1336

Podaci o odgovornosti

Yonghyun Hwang ; Schirner, Gunar ; Abdi, Samar ; Gajski, Daniel D.

engleski

Accurate timed RTOS model for transaction level modeling

In this paper, we present an accurate timed RTOS model within transaction level models (TLMs). Our RTOS model, implemented on top of system level design language (SLDL), incorporates two key features: RTOS behavior model and RTOS overhead model. The RTOS behavior model provides dynamic scheduling, inter-process communication (IPC), and external communication for timing annotated user applications. While the RTOS behavior model is running, all RTOS events, such as context switch and interrupt handling, are passed to RTOS over- head model to adopt the overhead during system execution. Our RTOS overhead model has processor- and RTOS-specific pre-characterized overhead information to provide cycle approximate estimation. We demonstrate the applicability of our model using a multi-core platform executing a JPEG encoder. Experimental results show that the proposed RTOS model provides the high accuracy, 7% off compared to on-board measurements while simulating at speeds close to the reference C code.

scheduling; transaction processing; JPEG encoder; RTOS behavior model; RTOS speciflc precharacterized overhead information; accurate timed RTOS model; cycle approximate estimation; dynamic scheduling; interprocess communication; multicore platform; system level design language; transaction level modeling; Application software; Context modeling; Delay estimation; Dynamic scheduling; Performance analysis; Scalability; Software performance; Switches; System-level design; Timing

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Podaci o prilogu

1333-1336.

2010.

objavljeno

Podaci o matičnoj publikaciji

Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010

Institute of Electrical and Electronics Engineers (IEEE)

Podaci o skupu

Design, Automation & Test in Europe Conference & Exhibition (DATE) 2010

predavanje

08.03.2010-12.03.2010

Dresden, Njemačka

Povezanost rada

Računarstvo