engleski

Automated Generation of VHDL Behavioral Models for Testing Purposes

One of the major tasks when designing a processor is testing the correctness of its behavioral model. Since simulation is a time consuming chore, it is better to perform a number of small tests, each of which checks a particular aspect of the processor. This approach is used in the modeling of a hard real-time processor when it became apparent that it was impractical to hand-code dozens of small assembler programs into VHDL models of the program memory. This paper describes the design of the respective assembler for generating VHDL models of component memories for the given processor, which are necessary for subsequent simulation.

behavioral modeling; design automation; hard real-time; VHDL

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