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Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system


Ćosić, Krešimir; Kopriva, Ivica; Kostić, Todor; Slamić, Miroslav; Volarević, Marijo
Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system // Simulation practice and theory, 7 (1999), 2; 107-123 (međunarodna recenzija, članak, znanstveni)


Naslov
Design and implementation of a hardware-in-the-loop simulator for a semi-automatic guided missile system

Autori
Ćosić, Krešimir ; Kopriva, Ivica ; Kostić, Todor ; Slamić, Miroslav ; Volarević, Marijo

Izvornik
Simulation practice and theory (0928-4869) 7 (1999), 2; 107-123

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
Hardware in the loop simulation; semi-automatic guided missile systme; Digital signal processors; Parallel processing;

Sažetak
Hardware in the loop (HIL) simulation based on modern digital signal processors is a cost-effective technology for the design and evaluation of various sophisticated weapon and industrial systems. The semi-automatic command to line of sight (SACLOS) missile system is one example of a complex weapon system for which modernisation is a very complex process.The presented HIL simulation examples illustrate the essential importance of HIL simulation technology for cost-effective, non-destructive prototype development of such SACLOS systems. The Importance of the simulation kernel consisting of 4 TMS320C40 digital signal processors for efficient real-time simulation of the implemented SACLOS subsystem models is also emphasised in this paper.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekt / tema
036024

Ustanove
Fakultet elektrotehnike i računarstva, Zagreb

Časopis indeksira:


  • Scopus


Uključenost u ostale bibliografske baze podataka:


  • The INSPEC Science Abstracts series
  • Current Content Electronics & Telecommunicatios