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SiGe dots as stressor material for strained Si devices

Over the last decade, strain-enhanced mobility has become an integral part of the roadmap for CMOS downscaling and various device architectures have been proposed to improve the way in which strain is introduced in the device channel [1, 2]. In this work, SiGe dots have been investigated as a stressor material, an approach that has the advantage of extreme scalability [3] and, by removing the dot at some stage of the processing, a silicon-on-nothing (SON) device architecture can be realized. The dots were grown by molecular-beam epitaxy (MBE) or chemical vapor deposition (CVD) on a silicon surface patterned with regular arrays of seedholes (Fig. 1) [4-6], the size and location of which were carefully controlled by high- resolution lithography. The individual SiGe dots grow in three dimensions by a Stranski-Krastanov mechanism and, without creating dislocations, a diameter as large as 250 nm with a Ge content of above 30% can be reached. By this 3D growth the SiGe dots can relax and when overgrown with a Si cap layer, biaxial tensile strain is induced in the Si that then can be used for electron mobility enhancement. For a thickness of the top Si layer of 30 nm, the strain in the region over the center of the dot can be up to 0.7%, as confirmed by measurements and supported by measurement- independent simulations (Fig. 1) [7]. It would be feasible to introduce the SiGe dots in current CMOS processes if the dot is not submitted to high-temperature steps that may cause excessive intermixing of the Ge from the dot with the surrounding Si and thus reduce the strain levels. This would mainly mean that the dot should be removed early in the process. Instead of doing this we developed a low-complexity, dedicated n- channel MOSFET process (Fig. 2) in which the dot was preserved throughout and the temperature after epitaxy was kept below 400°C [8]. To achieve ultrashallow, low-resistance source/drain regions that are contained within the 30 nm thick Si top layer, excimer-laser annealing (ELA) in full-melt mode is applied to the S/D implants while a metal gate-stack acts as a self-aligned masking layer. The location and dimensions of the device channel are controlled by electron-beam (EB) lithography, while the remaining lithography steps are performed with i-line optical lithography. To reduce the number of EB steps, the main part of the gate and channel is defined in a single lithography step, which leaves a gated region outside of the dot structure (Fig. 2). Very good, reproducible I-V device characteristics were achieved with the basic laser-anneal/metal- gate process flow when relaxed dimensions were used. When processed on the SiGe dots, significant variation of the characteristics appeared as a consequence of the nanoscale device dimensions but the overall results show a measurable performance advantage for the dot devices as compared to devices processed in parallel outside of the regular array of SiGe dots. The achievable current improvement has also been theoretically calculated using the measured strain levels as input.

MOSFETs; strain-enhanced mobility; laser annealing; low-temperature process

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