engleski

Electrical characterization of Si-SiO2 structures

Although many studies on electrical properties of MOS structures containing nanocrystals have been reported recently, there are only few works on the electrical behavior of the nanocrystals distributed very close to the oxide-semiconductor interface where the interface traps are present. The question how does those traps (i.e. fast traps), as well as the fixed charges in the oxide at the vicinity of the interface (i.e. slow traps) affect the charge storage in the nanocrystals, is still unanswered. In order to apply DLTS for studying the MOS structures containing the nanocrystals it is necessary to obtain and analyze DLTS results on “pure” MOS structures. We have presented a study of Si-SiO2 structures by means of capacitance – voltage (C-V) and deep level transient spectroscopy (DLTS) techniques. The phosphorous-doped (100) Si substrate with a 50 nm thick thermally grown oxide has been used in this study. We have shown that with different voltage conditions it is possible to study selected regions at and near the Si-SiO2 interface. The interface traps related to the Pb centers, distributed around 0.29 eV below the conduction band, have been observed. A mid-gap trap, located around 0.47 eV has also been detected. This trap has been observed only for the voltage conditions that lead to the inversion, but not too strong inversion. We believe that measured DLTS signal is affected by the minority carriers, i.e. holes. The influence of hydrogen is discussed.

Si-SiO2 interface; MOS; DLTS

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