engleski

Optimization of Stress Distribution in Sub-45 nm CMOS Structures

The impact of stress on electrical characteristics for sub-45 nm CMOS is examined. Analyzed stress sources are STI, deposited oxide cover layer and gate spacers. Stress type and values from these sources are manipulated in order to get optimal influence on electrical characteristics. Optimal stress parameters for nMOS are 2 GPa of intrinsic stress in STI and deposited cover layer, while for pMOS are -2 GPa in STI and deposited cover layer and 2 GPa in spacers. With these optimal parameters maximum ION current increase for 25 nm channel length structure is 29.3 % for nMOS and 105.6 % for pMOS transistors. There is no large influence of stress on DIBL effect and S factor.

CMOS; stress; shallow-trench isolation; gate spacers

nije evidentirano