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Power MOS Transistors Integrated in Standard CMOS Technology without any Increase in Process Complexity

In this paper, we developed power MOS structures where the drift region is fabricated by using the process steps that already exist in CMOS baseline technology, such as, LDD and/or n-well region together with LOCOS isolation and p^+ implantation. Five different structures fabricated in a standard 0.35μ m CMOS technology are examined by measurements and simulations and the effect of various technology parameters on device characteristics are analyzed. The optimum power MOS structure has B_VDS=20V, R_ON=9.4kΩ μ m and I_ON=220μ A/μ m, which correspond to the changes of +203%, +213% and – 46%, respectively, comparing to standard nMOS transistor.

power MOS transistors; 0.35um technology; breakdown; numerical simulations

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