engleski

Stress Effect in Ultra-Narrow FinFET Structures

The impact of standard FinFET process steps on the stress in the active part of transistor is examined. Additional stress is imported in structures by cap deposition that contains intrinsic stress of -400 megapascals. The stress magnitude and direction with respect to current flow are analyzed for wide-fin devices down to ultra-narrow fins of 2nm. Stress values from -400 to 200 megapascals are prevailing in structures, while stress maximums reach up to 10 gigapascals. Stress effect is included in electrical characteristics simulations. Results show current increase for nMOS of around 7% and the current change between -3% and +4% for pMOS. Possible current increase, with maximum stress influence, for nMOS is 30% and for pMOS is around 15%.

FinFET; stress effect; ultra-narrow body; numerical simulations

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