engleski

Series-Voltage Noise Margin of CMOS

The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in a system, whilst still operating correctly. In this work the methods of determining the static and dynamic series-voltage noise margins and the obtained results for CMOS are presented.

static series-voltage noise margin; dynamic series-voltage noise margin; CMOS

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