engleski

Process and Device BiCMOS Design

This paper discusses process design and device performance of the 1.0 *m BiCMOS technology. The basic features are: self-aligned buried layers, deep trench isolation, selectively implanted collector, self-aligned double-polysilicon bipolar npn transistor and light drain doping. The design is made with the two-dimensional process and device simulations. The absolute values of nMOS and pMOS transistor threshold voltages are adjusted to about 0.7 V to suit the 3.3 V supply voltage. *=micro

process design; device performance; BiCMOS; simulation

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