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ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters


Švedek, Tomislav; V.Ivančić
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters // IEE Proceedings E (Computers and Digital Techniques), 136 (1989), 450-455 (podatak o recenziji nije dostupan, članak, znanstveni)


Naslov
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters

Autori
Švedek, Tomislav ; V.Ivančić

Izvornik
IEE Proceedings E (Computers and Digital Techniques) (1350-2387) 136 (1989); 450-455

Vrsta, podvrsta i kategorija rada
Radovi u časopisima, članak, znanstveni

Ključne riječi
ASIC; test sequence; testability; asynchronous counters

Sažetak
The parallel/serial test procedure for application-specific integrated circuit (ASIC) logic surrounding embedded asynchronous counters is proposed, which increases counter controllability and observability and reduces test sequence length. Optimisation of counter partitioning and test sequence generation is carried out with the CAD program COUNTESS. For optimal partitioning COUNTESS calculates both the test hardware overhead and the minimum number of test cycles

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Profili:

Avatar Url Tomislav Švedek (autor)

Citiraj ovu publikaciju

Švedek, Tomislav; V.Ivančić
ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters // IEE Proceedings E (Computers and Digital Techniques), 136 (1989), 450-455 (podatak o recenziji nije dostupan, članak, znanstveni)
Švedek, T. & V.Ivančić (1989) ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters. IEE Proceedings E (Computers and Digital Techniques), 136, 450-455.
@article{article, author = {\v{S}vedek, T. and V.Ivan\v{c}i\'{c}}, year = {1989}, pages = {450-455}, keywords = {ASIC, test sequence, testability, asynchronous counters}, journal = {IEE Proceedings E (Computers and Digital Techniques)}, volume = {136}, issn = {1350-2387}, title = {ASIC test sequence minimisation by built-in testability in logic surrounding embedded binary asynchronous counters}, keyword = {ASIC, test sequence, testability, asynchronous counters} }