Problems in PLD Implementation of All-digital DLL (CROSBI ID 534954)
Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija
Podaci o odgovornosti
Matić, Tomislav ; Švedek, Tomislav ; Herceg, Marijan
engleski
Problems in PLD Implementation of All-digital DLL
Problems encountered in the implementation of an all-digital delay-locked loop (DLL) in programmable logic devices (PLD) are presented. All parts of a DLL are only created by discrete digital elements. A digital controlled delay line (DCDL) consists of digital controlled delay elements (DCDE) realized by a number of LCELLs (basic delay elements in ALTERA's PLD). An analog charge pump (CP) and a loop filter (LF) in the proposed circuit are replaced with a 3-bit UP/DOWN/HOLD counter. The proposed DLL is implemented and tested in the ALTERA PLD chip EPM7128SLI10.
Programmable Logic Device (PLD); All-digital DLL; Digital Controlled Delay Line
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Podaci o prilogu
1107-1110.
2008.
objavljeno
Podaci o matičnoj publikaciji
2008 3rd International Symposium on Communications, Control and Signal Processing (ISCCSP 2008)
Debono, Carl J. ; Gabbouj, Moncef
Institute of Electrical and Electronics Engineers (IEEE)
978-1-4244-1688-2
Podaci o skupu
2008 3rd International Symposium on Communications, Control and Signal Processing (ISCCSP 2008)
poster
12.03.2008-14.03.2008
San Ġiljan, Malta