engleski

Interconnect Delay Time Estimation

In a modern integrated circuits the delay time caused by gate and interconnects lines has great influence on circuit performance. In recent time interconnect has become parameter that can not be neglected. An adequate model for interconnect should be used together with an accurate and efficient model for delay time calculation. In this paper the interconnect wire has been modeled as a lump RC tree, with the various number of RC segments. Two models have been considered for delay time calculation, Elmore model and Asymptotic Waveform Evaluation (AWE) moment matching model. The obtained results have been compared with the SPICE analysis. It is shown that the AWE method that uses only few dominant poles is giving very good results.

integrated circuits; interconect delay; Elmore model; assymptotic waveform; evaluation moment; matching model; SPICE analysis

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