engleski

Metastability Characteristics Testing for Programmable Logic Design

The paper describes the problems associated with the phenomena of metastability in clock edge-triggered flip-flop designs in PLD (Programmable Logic Devices) architecture. The metastability probability, which is dependent on functionality speed, characteristics of integrated circuit technology, design methodology and effects of environmental conditions is discussed. The evaluation of the MTBF (Mean Time Between Failure) characteristics of PLD is done, based on the propagation delay distribution measurement of bistable output in the circumstances of deliberately inducing metastable behaviour. The testing results help in design, examine and to predict required MTBF in logic circuits design targeted for PLD. The proper design methodology that would help to virtually overcome the metastability problem is discussed.

time delay ; metastability ; reliability ; testing

Field-Programmable Logic : smart applications, new paradigms and compilers ; proceedings : 6th International Workshop on Field Programmable Logic and Applications : FPL '96 ; Sep. 23 - 25, 1996, Darmstadt, Germany ; ISBN 3-540-61730-2