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BDD complexity analysis of multiplier circuits (CROSBI ID 507354)

Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija

Grudenić, Igor ; Bogunović, Nikola BDD complexity analysis of multiplier circuits // Proceedings of the Joint Conferences Computers in Technical systems and Intelligent systems / Budin, Leo ; Ribarić, Slobodan (ur.). Rijeka: Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO, 2005. str. 31-34-x

Podaci o odgovornosti

Grudenić, Igor ; Bogunović, Nikola

engleski

BDD complexity analysis of multiplier circuits

The equivalence of Boolean functions is an important issue in hardware design. In order to check the equivalence of two combinatorial circuits SAT solvers and BDD based algorithms are used. For complex hardware designs efficient BDD manipulation algorithms must be employed. There is a number of industrial combinatorial circuitry for which BDD representation explodes exponentially in the number of inputs. An example of such a circuitry is multiplier that is known to have no efficient BDD representation regardless of the employed variable ordering. In this paper we analyze some important properties of the BDD representation of multipliers, as well as the complexity of the involved computations

formal verification; symbolic model checking; BDDs; multiplier complexity

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Podaci o prilogu

31-34-x.

2005.

objavljeno

Podaci o matičnoj publikaciji

Proceedings of the Joint Conferences Computers in Technical systems and Intelligent systems

Budin, Leo ; Ribarić, Slobodan

Rijeka: Hrvatska udruga za informacijsku i komunikacijsku tehnologiju, elektroniku i mikroelektroniku - MIPRO

Podaci o skupu

Computers in Technical Systems

predavanje

30.05.2005-03.06.2005

Opatija, Hrvatska

Povezanost rada

Računarstvo