engleski

Propagation Time Optimization Using Transistor Sizing

The CMOS inverter parasitic capacitances have been analytically estimated for the cascaded inverter pair. The optimal transistor ratio has been determined to minimize the inverter propagation delay. The chain of gradually increasing CMOS inverters have been analyzed in order to minimize the propagation delay when driving a large capacitive load. The calculation of the optimal sizing factor and the optimal number of stages of the chain has been compared for two cases: the simple one with ignoring the self-loading inverter capacitance and the more accurate that takes into account this capacitance. The PSpice analysis, based on 0.25 micron CMOS technology, has shown that the inclusion of the self-loading inverter capacitance offers better results.

CMOS inverter; parasitic capacitances; propagation delay; PSpice

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