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VLSI Circuit Partition Using Simulated Annealing Algorithm (CROSBI ID 496795)

Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija

Kolar, Dalibor ; Divković Pukšec, Julijana ; Branica, Ivan VLSI Circuit Partition Using Simulated Annealing Algorithm // Proceedings / MELECON 2004 / Matijašević, Maja ; Pejčinović, Branimir ; Tomšić, Željko et al. (ur.). Zagreb: Institute of Electrical and Electronics Engineers (IEEE), 2004. str. 205-208-x

Podaci o odgovornosti

Kolar, Dalibor ; Divković Pukšec, Julijana ; Branica, Ivan

engleski

VLSI Circuit Partition Using Simulated Annealing Algorithm

In this work the two way partitioning of a circuit represents as a graph, was made using simulated annealing procedure. The parameters used in annealing process: initial temperature, cooling rate and the time of a process, given as a number of calculations, are chenged and its influence on the cost function (number of nets cut by partition) are described. With a proper choice of the initial temperature and the cooling rate we can obtain a good, not necessarily the best solution, not spending too much time to find out. Procedure was tested on an example with a 1000 components connected by 300 nets. We conclude that all parameters depend on a circuit itself (its size and number of interconnections).

partitioning; cost function; interconnections

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Podaci o prilogu

205-208-x.

2004.

objavljeno

Podaci o matičnoj publikaciji

Proceedings / MELECON 2004

Matijašević, Maja ; Pejčinović, Branimir ; Tomšić, Željko ; Butković, Željko

Zagreb: Institute of Electrical and Electronics Engineers (IEEE)

Podaci o skupu

The 12th IEEE Mediterranean Electrotechnical Conference

predavanje

12.05.2004-15.05.2004

Dubrovnik, Hrvatska

Povezanost rada

Elektrotehnika