hrvatski

Električka svojstva prospojnih metalnih vodova u VLSI integriranim sklopovima

The chip interconnect parasitic elemetns and their influcence on the integrated circuits were being presented in this paper. The RC, RLC and trasmission line models were also described in aspect of time delay and crosstalk analysis. A characterisitc structure was analized using FastHenry and FastCap extraction applications and the results were used to model the Spice RLC based circuit. This work also describes some methods for minimizing on-chip crosstalk and time delay and optimizing the routing of the chips interconnect.

VLSI; prospoji; prospajanje; metalizacija; vrijeme kašnjenja; preslušavanje; RC; RLC; prijenosne linije

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