engleski

Inductive Influence on Propagation Delay of IC Interconnect

In modern high-speed microprocessors interconnections significantly affect the chip performance. Thus far, interconnect was modeled as an RC circuit, whether lumped or distributed. However, as speeds increase, interconnect inductances need to be included in the interconnect model. To test the behaviour of the typical VLSI interconnect, the 8-bit signal bus inside the power/ground grid is examined. The bus length was varied from 200 &#61549 ; m to 2000 &#61549 ; m. Different sets of input data-patterns were simulated to determine the propagation delay worst-case input vector. From the obtained data it is confirmed that the capacitance still has the most significant impact on the delay, but as the line lengths increase the inductance becomes more significant. Short lines can be modeled using the RC model but for longer lines inductance has to be included in the model.

interconnect; delay; crosstalk; extraction

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