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FPGA Design and Implementation of Driving Lane Detection on Zynq-7000 SoC

Number of different Advanced Driving Assistant Systems (ADAS) are implemented in modern vehicles. One of the important ADAS is lane departure warning system which warns driver when lane switching is occurring unintentionally. Integral part of such system is a lane detection algorithm based on front-view camera images. In this paper, an algorithm for detecting lane markings from images is designed and implemented in FPGA technology on Zynq-7000 System-on-Chip (SoC) using VHDL. The algorithm is based on traditional computer vision techniques to obtain lane markings and detect driving lane. The algorithm evaluation was performed on images of different resolution in various conditions. The high performance has been achieved in terms of lane detection, but improvements are needed in terms of algorithm execution speed.

FPGA: VHDL ; lane detection ; Zynq-700 SoC

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