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Layout-Dependent Noise Performance of Single- Photon Avalanche Diodes in 180 nm High-Voltage CMOS Technology

The paper describes the implementation and characterization of single-photon avalanche diodes (SPADs) fabricated in a commercial 180 nm high voltage (HV) bipolar-CMOS-DMOS (BCD) technology. The SPAD structures utilize a deep, low-doped p-n junction as the avalanche multiplication layer, exploiting the high-voltage implant layers available in the technology. Technology computer aided design (TCAD) simulations are performed to ensure that breakdown occurs in the active region of the device and to estimate the breakdown voltage and dark count rate (DCR). The devices are fabricated with different sizes and a circular, octagonal or square layout. The SPADs are characterized in terms of current-voltage (I-V) curves and dark count rates, both on bare dies as well as on dies bonded to a printed circuit board (PCB), by connecting them to an offchip passive quenching circuit. Afterpulsing probability is analyzed by studying the distribution of interarrival times of dark pulses and comparing it to that of an ideal Poisson process. The circular and octagonal devices exhibit state-of-the-art noise performance with DCRs as low as 0.47 Hz/um2 at an excess voltage of 5 V, whereas the DCR of square structures increases by up to 2.7 times, partly due to afterpulsing effects at high excess voltages.

single photon avalanche diodes (SPADs), dark count rate (DCR), afterpusling, photodetectors, CMOS image sensors, photon counting, TCAD simulations, layout

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