engleski

Model checking of concurrent system with SDL/sup --/ specification

It is well known that the best results regarding concurrent system design are obtained when design errors are found in the earliest possible phase. For that purpose system specification is verified through model checking. We try to hide, as much as possible, the model checking formalism from the designers viewpoint. First, a system is modeled as a set of processes described formally as an extended finite state machine within the SDL/sup --/ language. Such a description is translated into the model checker, SPIN, where the desired properties are verified. Special attention is given to the possibility of modeling various types of transitions and to a definition of the tool where model checking is performed. With such an approach the designer can have the, SDL/sup --/ specification verified against the desired properties.

specification languages, formal specification, formal verification, multiprocessing systems, finite state machines, reachability analysis

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