Generalized Parallel/Serial Test Procedure for Counters in Digital Low Complexity ASICs (CROSBI ID 490576)
Prilog sa skupa u zborniku | izvorni znanstveni rad | međunarodna recenzija
Podaci o odgovornosti
Švedek, Tomislav ; Švedek, Velimir
engleski
Generalized Parallel/Serial Test Procedure for Counters in Digital Low Complexity ASICs
This paper proposes a generalized Parallel/Serial Test Procedure for testing of all kinds of long counters embedded in the surrounding logic. Its advantages and drawbacks are discussed, and an example of 7-order of magnitude reduction of the test sequence is given.
DFT; Parallel/Serial Procedure; ASIC; counter
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Podaci o prilogu
375 - 378-x.
2002.
objavljeno
Podaci o matičnoj publikaciji
Proceedings of the INES 2002 - IEEE 375 - 378
Lovrenčić, Alen ; Rudas, J, Imre
Opatija: Fakultet organizacije i informatike Sveučilišta u Zagrebu
Podaci o skupu
IEEE International Conference on Intelligent Engineering Systems
predavanje
01.01.2002-01.01.2002
Opatija, Hrvatska