Napredna pretraga

Pregled bibliografske jedinice broj: 111986

Static Series-Voltage Noise Margins of CBL, CSL and CMOS


Szabo, Aleksandar; Butković, Željko
Static Series-Voltage Noise Margins of CBL, CSL and CMOS // Proc. of ICECS 2002
Dubrovnik, Hrvatska: IEEE, 2002. str. 587-590 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


Naslov
Static Series-Voltage Noise Margins of CBL, CSL and CMOS

Autori
Szabo, Aleksandar ; Butković, Željko

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Proc. of ICECS 2002 / - Dubrovnik, Hrvatska : IEEE, 2002, 587-590

Skup
The 9th International Conference on Electronics, Circuits and Systems

Mjesto i datum
Dubrovnik, Hrvatska, 15-18.09.2002

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
noise margin; static series-voltage noise margin; CBL; CSL; CMOS

Sažetak
The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in the system, whilst still operating correctly. In this work the static series-voltage noise margin of CBL (Current-Balanced Logic), CSL (Current-Steering Logic) and CMOS are determined and compared.

Izvorni jezik
Engleski

Znanstvena područja
Elektrotehnika



POVEZANOST RADA


Projekt / tema
0036001
0036027

Ustanove
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Aleksandar Szabo (autor)

Avatar Url Željko Butković (autor)

Citiraj ovu publikaciju

Szabo, Aleksandar; Butković, Željko
Static Series-Voltage Noise Margins of CBL, CSL and CMOS // Proc. of ICECS 2002
Dubrovnik, Hrvatska: IEEE, 2002. str. 587-590 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Szabo, A. & Butković, Ž. (2002) Static Series-Voltage Noise Margins of CBL, CSL and CMOS. U: Proc. of ICECS 2002.
@article{article, year = {2002}, pages = {587-590}, keywords = {noise margin, static series-voltage noise margin, CBL, CSL, CMOS}, title = {Static Series-Voltage Noise Margins of CBL, CSL and CMOS}, keyword = {noise margin, static series-voltage noise margin, CBL, CSL, CMOS}, publisher = {IEEE}, publisherplace = {Dubrovnik, Hrvatska} }