Design of frequency divider and phase-frequency detector in 180-nm CMOS technology (CROSBI ID 433477)
Ocjenski rad | diplomski rad
Podaci o odgovornosti
Žamboki, Andro
Barić, Adrijan
engleski
Design of frequency divider and phase-frequency detector in 180-nm CMOS technology
Design of the parts of a phase locked loop (PLL) called "Duty cycle control" and "Level shifter" in CMOS 180 nm integrated technology. The system has to have the ability to shift the input clock signal from a lower voltage domain to a higher and ensure that the duty cycle of the output clock signal is exactly 50%. The system has to work in all possible worst case corners. Top level simulations of the whole PLL have to be performed and they need to demonstrate the PLL's ability to follow the input frequency and resist outside disturbances.
phase locked loop ; integrated circuits ; integrated electronics ; CMOS ; circuit simulations ; duty cycle ; level shifter ; duty cycle control
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Podaci o izdanju
42
07.07.2020.
obranjeno
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Fakultet elektrotehnike i računarstva
Zagreb