Pretražite po imenu i prezimenu autora, mentora, urednika, prevoditelja

Napredna pretraga

Pregled bibliografske jedinice broj: 1059558

An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator


Cobrnic, Mate; Duspara, Alen; Dragic, Leon; Piljic, Igor; Mlinaric, Hrvoje; Kovac, Mario
An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator // Parallel Processing and Applied Mathematics / Wyrzykowski, Roman ; Deelman, Ewa ; Dongarra, Jack ; Karczewski, Konrad (ur.).
Bialystok, Poljska: Springer, Cham, 2020. str. 199-208 doi:10.1007/978-3-030-43229-4_18 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)


CROSBI ID: 1059558 Za ispravke kontaktirajte CROSBI podršku putem web obrasca

Naslov
An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator

Autori
Cobrnic, Mate ; Duspara, Alen ; Dragic, Leon ; Piljic, Igor ; Mlinaric, Hrvoje ; Kovac, Mario

Vrsta, podvrsta i kategorija rada
Radovi u zbornicima skupova, cjeloviti rad (in extenso), znanstveni

Izvornik
Parallel Processing and Applied Mathematics / Wyrzykowski, Roman ; Deelman, Ewa ; Dongarra, Jack ; Karczewski, Konrad - : Springer, Cham, 2020, 199-208

ISBN
978-3-030-43228-7

Skup
International Conference on Parallel Processing and Applied Mathematics

Mjesto i datum
Bialystok, Poljska, 8-11.09.2019

Vrsta sudjelovanja
Predavanje

Vrsta recenzije
Međunarodna recenzija

Ključne riječi
Integer Discrete Cosine Transform (DCT) ; High Efficiency Video Coding (HEVC) ; Field-Programmable Gate Array (FPGA) ; Pipelined architecture

Sažetak
In this paper is presented an area efficient reusable architecture for integer one dimensional Discrete Cosine Transform (1D DCT) with adjustable transform sizes in High Efficiency Video Coding (HEVC). Optimization is based on exploiting of symmetry and subset properties of the transform matrix. The proposed multiply-accumulate architecture is fully pipelined and applicable for all transform sizes. It provides the interface over which the processing system can control the datapath of the transform process and the synchronization channel that enables the system to receive the feedback information about utilization from the device. An intuitive line approach for calculating transform coefficients for all transform sizes was used instead of the commonly applied recursive decomposition approach. This approach simplifies disabling of lines that are not employed for a particular transform size. The proposed architecture is implemented on the FPGA platform, can operate at 407, 5 MHz, achieves throughput of 815 Msps and can support encoding of a 4K UHD@30 fps video sequence in real time.

Izvorni jezik
Engleski

Znanstvena područja
Računarstvo



POVEZANOST RADA


Projekti:
EK-H2020-826647 - Inicijativa za Europski procesor (EPI SGA1) (Kovač, Mario, EK - H2020-SGA-LPMT-2018) ( POIROT)

Ustanove:
Fakultet elektrotehnike i računarstva, Zagreb

Profili:

Avatar Url Mario Kovač (autor)

Avatar Url Alen Duspara (autor)

Avatar Url Hrvoje Mlinarić (autor)

Avatar Url Mate Čobrnić (autor)

Poveznice na cjeloviti tekst rada:

doi link.springer.com

Citiraj ovu publikaciju:

Cobrnic, Mate; Duspara, Alen; Dragic, Leon; Piljic, Igor; Mlinaric, Hrvoje; Kovac, Mario
An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator // Parallel Processing and Applied Mathematics / Wyrzykowski, Roman ; Deelman, Ewa ; Dongarra, Jack ; Karczewski, Konrad (ur.).
Bialystok, Poljska: Springer, Cham, 2020. str. 199-208 doi:10.1007/978-3-030-43229-4_18 (predavanje, međunarodna recenzija, cjeloviti rad (in extenso), znanstveni)
Cobrnic, M., Duspara, A., Dragic, L., Piljic, I., Mlinaric, H. & Kovac, M. (2020) An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator. U: Wyrzykowski, R., Deelman, E., Dongarra, J. & Karczewski, K. (ur.)Parallel Processing and Applied Mathematics doi:10.1007/978-3-030-43229-4_18.
@article{article, year = {2020}, pages = {199-208}, DOI = {10.1007/978-3-030-43229-4\_18}, keywords = {Integer Discrete Cosine Transform (DCT), High Efficiency Video Coding (HEVC), Field-Programmable Gate Array (FPGA), Pipelined architecture}, doi = {10.1007/978-3-030-43229-4\_18}, isbn = {978-3-030-43228-7}, title = {An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator}, keyword = {Integer Discrete Cosine Transform (DCT), High Efficiency Video Coding (HEVC), Field-Programmable Gate Array (FPGA), Pipelined architecture}, publisher = {Springer, Cham}, publisherplace = {Bialystok, Poljska} }
@article{article, year = {2020}, pages = {199-208}, DOI = {10.1007/978-3-030-43229-4\_18}, keywords = {Integer Discrete Cosine Transform (DCT), High Efficiency Video Coding (HEVC), Field-Programmable Gate Array (FPGA), Pipelined architecture}, doi = {10.1007/978-3-030-43229-4\_18}, isbn = {978-3-030-43228-7}, title = {An Area Efficient and Reusable HEVC 1D-DCT Hardware Accelerator}, keyword = {Integer Discrete Cosine Transform (DCT), High Efficiency Video Coding (HEVC), Field-Programmable Gate Array (FPGA), Pipelined architecture}, publisher = {Springer, Cham}, publisherplace = {Bialystok, Poljska} }

Časopis indeksira:


  • Scopus


Citati:





    Contrast
    Increase Font
    Decrease Font
    Dyslexic Font