engleski

Design Methodology of an On–Chip Inductor in 180 nm CMOS Technology

This paper presents the design methodology for an on–chip inductor in 180 nm CMOS technology, intended for a fully integrated LC oscillator. The design method uses the model based on the physical interpretation of the inductor, and optimizes the design with respect to the Q –factor. Resulting from the optimization procedure, the inductor is designed for the on–chip LC resonator, having the nominal inductance value of $L_{;S};=2.62$ nH and Q –factor of 5.42 at 1 GHz. Finally, the designed inductor is verified by the EM simulations, and the results are compared to the physical model used for the optimization.

LC resonator ; on–chip inductor ; electromagnetic simulations ; Q–factor

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